1. Field of the Invention
The present invention relates to a semiconductor structure, and more particularly, to an epitaxial semiconductor fin structure.
2. Description of the Prior Art
Epitaxial structures are prevalently used in a wide variety of semiconductor applications. For example, the prior art usually forms an epitaxial layer such as an epitaxial silicon germanium (hereinafter abbreviated as SiGe) layer in a single crystal substrate by performing a selective epitaxial growth (hereinafter abbreviated as SEG) method. Because lattice constant of the epitaxial SiGe layer is larger than that of the silicon substrate, a strain stress is generated to the meta-oxide semiconductor (hereinafter abbreviated as MOS) transistor device. Accordingly, carrier mobility in the channel region is improved and the speed of the MOS transistor device is increased.
Although the epitaxial structures efficiently improve device performance, it increases complexity of the semiconductor fabrication and difficulties of process control. For example, though higher Ge concentration in the epitaxial SiGe layer improves device performances, dislocation defects usually occur in the higher Ge concentration and/or thicker epitaxial SiGe layer due to the lattice mismatch between the materials. The dislocation defect unwantedly reduces the strain stress. Therefore, it is getting more and more difficult to design and fabricate semiconductor devices having epitaxial structures.
Accordingly, though the epitaxial structure is able to improve the device performance, it is always in need to provide semiconductor devices as expected when the progress of semiconductor manufacturing technology is improved and complexity of the products is increased.